This can be a lot of extra work for a complex machine, but can save lots of debugging during start up which could result in great savings. This way, they are still there in the input map (or output map) to remind you that they need a real world assignment in the finished project, and you can right click and "toggle bit" to test the main program.Īlso, you can add a ladder file for testing purposes that can simulate the I/O, for example if a motor starter output bit is turned on, then 3 seconds later a limit switch input should come on. Any I/O that can't be addressed in the test setup can be listed like this: In those two ladder files, you will map the real I/O to internal bits which are used in the main logic of the PLC. create a ladder file called "outputs" and make it the last JSR in the main program. create a ladder file called "Inputs" and make a JSR to it at the beginning of the main program.Ģ. If you need to use the real processor for testing, here is what I would do:ġ. If you can get RSLogix 500 Emulate, then it may allow you to do much of your logic testing, although it will not emulate PID loops and there are limits to what it can do with communication.
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